stk_arch_arm-cortex-m.h

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/*
 * SuperTinyKernel(TM) RTOS: Lightweight High-Performance Deterministic C++ RTOS for Embedded Systems.
 *
 * Source: https://github.com/SuperTinyKernel-RTOS
 *
 * Copyright (c) 2022-2026 Neutron Code Limited <stk@neutroncode.com>. All Rights Reserved.
 * License: MIT License, see LICENSE for a full text.
 */
 
#ifndef STK_ARCH_ARM_CORTEX_M_H_
#define STK_ARCH_ARM_CORTEX_M_H_
 
#include "stk_common.h"
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE != 0)
    #include <arm_cmse.h> // for ARM TrustZone
#endif

#ifndef STK_ARCH_ARMV6_M
    #if defined(__ARM_ARCH_6M__)
        #define STK_ARCH_ARMV6_M (1)
    #else
        #define STK_ARCH_ARMV6_M (0)
    #endif
#else
    #if (STK_ARCH_ARMV6_M == 0) && defined(__ARM_ARCH_6M__)
        #error "STK_ARCH_ARMV6_M must be defined as 1 on ARMv6-M platform!"
    #endif
#endif

#ifndef STK_ARCH_ARMV7_M
    #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
        #define STK_ARCH_ARMV7_M (1)
    #else
        #define STK_ARCH_ARMV7_M (0)
    #endif
#else
    #if (STK_ARCH_ARMV7_M == 0) && (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
        #error "STK_ARCH_ARMV7_M must be defined as 1 on ARMv7-M platform!"
    #endif
#endif

#ifndef STK_ARCH_ARMV8_M
    #if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
        #define STK_ARCH_ARMV8_M (1)
    #else
        #define STK_ARCH_ARMV8_M (0)
    #endif
#else
    #if (STK_ARCH_ARMV8_M == 0) && (defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__))
        #error "STK_ARCH_ARMV8_M must be defined as 1 on ARMv8-M platform!"
    #endif
#endif
 
// Expect at least one supported target architecture.
#if !STK_ARCH_ARMV6_M && !STK_ARCH_ARMV7_M && !STK_ARCH_ARMV8_M
    #error "Unsupported ARM architecture target!"
#endif
 
// Enforce single active target architecture state.
#if (STK_ARCH_ARMV6_M + STK_ARCH_ARMV7_M + STK_ARCH_ARMV8_M) > 1
    #error "Multiple STK_ARCH_ARMvX flags active simultaneously! Check build environment definitions."
#endif

#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
    #define __stk_tz_nsc_entry __attribute__((cmse_nonsecure_entry))
#else
    #define __stk_tz_nsc_entry
#endif

#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
    #define __stk_tz_ns_call __attribute__((cmse_nonsecure_call))
#else
    #define __stk_tz_ns_call
#endif

#define STK_TZ_NSC_GATEWAY extern "C" __stk_tz_nsc_entry
 
// ARM TrustZone Non-Secure binary configuration validation.
#ifdef _STK_CORTEX_M_TRUSTZONE_NON_SECURE
#if !STK_TZ_NON_SECURE
    #error "Do not use -cmse compiler flag for Non-Secure binary compilation!"
#endif
#endif
 
// Task MPU is supported only when MPU is enabled globally.
#if STK_MPU_STACK_GUARD && !STK_MPU
    #error "Enable MPU support (STK_MPU=1) to use per-task MPU feature (STK_MPU_STACK_GUARD=1)!"
#endif

#ifndef STK_CORTEX_M_MPU_REGIONS_MAX
    #define STK_CORTEX_M_MPU_REGIONS_MAX (8U)
#endif

#ifndef STK_CORTEX_M_SVCALL_ISR_PRIORITY
    #define STK_CORTEX_M_SVCALL_ISR_PRIORITY (0U)
#endif

static __stk_forceinline void __stk_dmb() { __asm volatile("dmb sy" ::: "memory"); }

 
namespace stk {

class PlatformArmCortexM final : public IPlatform
{
public:
    STK_VIRT_DTOR ~PlatformArmCortexM() = default;
 
    void Initialize(IEventHandler *event_handler, IKernelService *service, uint32_t resolution_us, Stack *exit_trap) override;
    void Start() override;
    void Stop() override;
    void InitStack(EStackType stack_type, Stack *stack, IStackMemory *stack_memory, ITask *user_task) override;
    uint32_t GetTickResolution() const override;
    Cycles GetSysTimerCount() const override;
    uint32_t GetSysTimerFrequency() const override;
    void SwitchToNext() override;
    void ForceContextSwitch(TId id) override;
    void Sleep(Timeout ticks) override;
    bool SleepUntil(Ticks timestamp) override;
    EWaitResult Wait(ISyncObject *sync_obj, IMutex *mutex, Timeout timeout) override;
    void ProcessTick() override;
    void ProcessHardFault() override;
    void SetEventOverrider(IEventOverrider *overrider, bool non_secure) override;
    Word GetCallerSP() const override;
    TId GetTid() const override;
    Timeout Suspend() override;
    void Resume(Timeout elapsed_ticks) override;
    void SetCpuFrequency(uint8_t core_id, uint32_t frequency) override;
};

typedef PlatformArmCortexM PlatformDefault;
 
// Inline TLS via r9. Active when both STK_TLS and STK_TLS_PREFER_REGISTER are
// enabled. Requires -ffixed-r9 on all translation units containing task code
// (see GetTls/SetTls warnings below). If -ffixed-r9 is unavailable or
// undesirable, leave STK_TLS_PREFER_REGISTER disabled; the kernel will fall back
// to a memory-based TLS slot with a small additional load/store per access.
// =============================================================================
#if STK_TLS && STK_TLS_PREFER_REGISTER
// =============================================================================

static __stk_forceinline Word GetTls()
{
    Word tp;
    __asm volatile("MOV %0, r9" : "=r"(tp) : /* input: none */ : /* clobbers: none */);
    return tp;
}

static __stk_forceinline void SetTls(Word tp)
{
    __asm volatile("MOV r9, %0" : /* output: none */ : "r"(tp) : /* clobbers: none */);
}
 
// Notify stk_arch.h that we defined inline versions of GetTls/SetTls.
#define STK_INLINE_TLS (1)
 
// =============================================================================
#endif // STK_TLS_PREFER_REGISTER
// =============================================================================
 
namespace hw {

struct ExceptionFrame
{
    Word R0;
    Word R1;
    Word R2;
    Word R3;
    Word R12;
    Word LR;
    Word PC;
    Word xPSR;
};
 
} // namespace hw
 
// =============================================================================
#if STK_MPU
// =============================================================================

namespace hw {
namespace mpu {
 
#if STK_ARCH_ARMV8_M
 
// ARMv8-M MPU Variant (PMSAv8 Layout)

enum EMpuAccess : uint8_t
{
    ACCESS_NONE             = 0xFFU,  
 
    ACCESS_PRIV_RW_USER_NO  = (0x0U << 1U), 
    ACCESS_FULL             = (0x1U << 1U), 
    ACCESS_PRIV_RO_USER_NO  = (0x2U << 1U), 
    ACCESS_PRIV_RO_USER_RO  = (0x3U << 1U)  
};

enum EMpuExec : uint8_t
{
    EXEC_ALLOWED            = (0x0U << 0U), 
    EXEC_NEVER              = (0x1U << 0U)  
};

enum EMpuType : uint8_t
{
    TYPE_STRONGLY_ORDERED   = 0U, 
    TYPE_DEVICE             = 1U, 
    TYPE_NORMAL_NON_CACHE   = 2U, 
    TYPE_NORMAL_CACHEABLE   = 3U  
};

enum EMpuShare : uint8_t
{
    SHARE_NON               = (0x0U << 3U), 
    SHARE_OUTER             = (0x2U << 3U), 
    SHARE_INNER             = (0x3U << 3U)  
};
 
#else // !STK_ARCH_ARMV8_M
 
// Legacy ARMv7-M MPU Variant (PMSAv7 Layout)

enum EMpuAccess : uint32_t
{
    ACCESS_NONE             = 0xFFFFFFFFU,   
 
    ACCESS_HW_NO_ACCESS     = (0x0U << 24U), 
    ACCESS_PRIV_RW_USER_NO  = (0x1U << 24U), 
    ACCESS_PRIV_RW_USER_RO  = (0x2U << 24U), 
    ACCESS_FULL             = (0x3U << 24U), 
    ACCESS_PRIV_RO_USER_NO  = (0x5U << 24U), 
    ACCESS_PRIV_RO_USER_RO  = (0x6U << 24U)  
};

enum EMpuExec : uint32_t
{
    EXEC_ALLOWED            = (0x0U << 28U),
    EXEC_NEVER              = (0x1U << 28U)
};

enum EMpuType : uint32_t
{
    TYPE_STRONGLY_ORDERED   = 0x000000U, 
    TYPE_DEVICE             = 0x010000U, 
    TYPE_NORMAL_NON_CACHE   = 0x080000U, 
    TYPE_NORMAL_CACHEABLE   = 0x030000U  
};

enum EMpuShare : uint32_t
{
    SHARE_NON               = (0x0U << 18U), 
    SHARE_OUTER             = (0x1U << 18U), 
    SHARE_INNER             = (0x1U << 18U)  
};
 
#endif // STK_ARCH_ARMV8_M

enum EMpuConfigFlags : uint32_t
{
    MPU_CFG_NONE              = 0U,        
    MPU_CFG_PRIVILEGED_BG_MEM = (1U << 0), 
    MPU_CFG_IN_FAULTS         = (1U << 1), 
    MPU_CFG_CLEAR_ON_INIT     = (1U << 2), 
    MPU_CFG_NONSECURE_MPU     = (1U << 3)  
};
 
} // namespace mpu
} // namespace hw

struct MpuRegionConfig
{
    Word                addr;        
    size_t              size;        
    hw::mpu::EMpuAccess access_perm; 
    hw::mpu::EMpuType   mem_type;    
    hw::mpu::EMpuShare  share;       
    hw::mpu::EMpuExec   exec;        
};

 
// =============================================================================
#endif // STK_MPU
// =============================================================================

struct FaultContext
{
    struct Mpu
    {
        struct Region
        {
            Word RNR;  
            Word RBAR; 
            Word ATTR; 
        };
 
        Word   CTRL;  
    #if STK_ARCH_ARMV8_M
        Word   MAIR0; 
        Word   MAIR1; 
    #endif
        Region regions[STK_CORTEX_M_MPU_REGIONS_MAX]; 
    };
 
    hw::ExceptionFrame frame;       
    Word               CFSR;        
    Word               HFSR;        
    Word               MMFAR;       
    Word               BFAR;        
    Word               AFSR;        
    Word               CONTROL;     
    Word               EXC_RETURN;  
#if STK_MPU
    Mpu                mpu;         
    #if STK_ARCH_ARMV8_M && STK_TZ_SECURE
    Mpu                mpu_ns;      
    #endif
#endif
    bool               mmfar_valid; 
    bool               bfar_valid;  

    void Fill(const Word *stacked_regs, Word exc_return);
};
 
} // namespace stk
 
#endif /* STK_ARCH_ARM_CORTEX_M_H_ */